The present invention relates to electronic circuits, and, more particularly, to a circuit for generating a pulse signal substantially independent of voltage and/or temperature variations.
As is well known, reading of the cell contents of a semiconductor integrated electronic memory circuit is allowed by a predetermined operation sequence known as reading cycle. A reading cycle starts when the memory address of a cell to be read is presented to the input terminals of the memory circuit. An input stage detects the switching of an address located on such terminals, thus starting a reading operation. Row and column decoding circuits select the addressed memory word.
The circuit portion which is adapted to read the memory cell contents and convert the read analog data into digital data is referred to as sense amplifier or reading amplifier. The data detected by the sense amplifier is presented as an output by an output buffer stage.
Each of the above phases of the reading cycle should have a predetermined duration compatible with the memory access times provided by the memory circuit specifications. All the various phases of the reading cycle are clocked by synchronization pulses derived from a single main pulse called an Address Transition Detection (ATD) pulse. The ATD pulse is generated inside the memory circuit each time an address switching is detected on the input terminals.
The prior art provides for different examples of constant pulse generators using the principle of discharging a constant current capacity. One of the most considerable shortcomings of these circuits is due to the fact that the initial capacitance discharge takes place during the input pulse duration. If such a pulse is of short duration, the discharge is not complete and the circuit thus generates shorter pulses. Furthermore, such pulse generating circuits often need to be initialized during the power-on step of the system, thus often causing malfunctions.
The traditional ATD circuits are based on switching of a latch forced through two pull-down transistors which act on both sides of the latch. This approach is widely used both for its simplicity, as well as for its robustness.
In FIG. 1 a schematic example of the well-known ATD circuit is illustrated. These ATD circuits nevertheless introduce a problem of generating impulses having a duration dependent on the supply voltage or temperature. The latch inverters are made using certain transistors of the PMOS type with kp less than  less than kn. At the moment of switching of the input terminal IN, one of the two capacities charges itself approximately in a linear way and, upon reaching the inverter threshold to which it is connected, the latch switches. The other capacitance is instead discharged immediately due to NMOS pull-down transistors, which are structured in such a way as to behave like switches.
The main drawback of a circuit like the one previously illustrated is due to the fact that the charge of the capacitance on which the circuit operation is based, is strongly influenced by the supply voltage and by the temperature, which affects the threshold of the PMOS transistors.
An object of the present invention is to provide a pulse generator circuit, such as, for example, an ATD type pulse generator, whose circuit has both functional and structural characteristics able to overcome the drawbacks which still affect the approaches of the prior art.
One embodiment of the invention provides the use of a memory element, for example a flip-flop, to filter the enabling ATD signal and avoid the problem of the partial discharge of one of the capacitances associated with the latch structure. According to this embodiment, the invention relates to a circuit for generating a constant pulse signal from an enabling ATD input signal and which may comprise a latch structure connected between first and second circuit nodes, each node being coupled to a corresponding charge and discharge capacitance and being also connected to respective inputs of a logic gate. The circuit may also include a memory element coupled to the circuit nodes for filtering the enabling ATD signal and avoiding a partial discharge of one of the capacitances. The circuit may also use an output of the logic gate for generating the constant pulse signal independent of voltage and/or temperature variations affecting the enabling ATD signal.
The filtering action of the memory element forces its output to switch after receipt of an input ATD pulse. Such an output does not switch if the input pulse is too narrow. The inventive circuit is thus transparent to the amplitude of the input pulses. Since the memory element is a bistable, there is no need to initialize it at the power-on phase.